[Mar-20] Automated System-Level Co-design: Are We Finally Ready?
Hardware/software co-design is an old problem. After several decades of study, the most popular way now for co-design is still through manual hardware/software partitioning. The main challenges for automated system-level co-design are twofold: (a) The solution must consider a wide variety of hardware implementations of each region candidate for acceleration, exposing trade-offs in area versus performance and power/energy. (b) It must be capable to accurately model the entire system and all its components, for a realistic compile-time estimation of all design points, enabling to design globally optimal partitioning solutions under specific area or power budgets. In this talk, we present our latest research results to tackle these challenges. We first built analytical models of system power and performance that are only 5% away from gate-level evaluation results but are several orders of magnitude faster. Thus we can effectively prune away a large amount of inferior hardware design points and generate Pareto-optimal solution points. We then developed a flow that used an idea called parallelized profiling of regions of interests with dynamic phase convergence that enabled high-speed code-specific CPU software profiling support, achieving an average speedup of 42.7x and 323.1x comparing to Sniper and gem5 simulators respectively. Based on these new results, we then developed a hybrid approach based on mixing semi-random selection of hardware design points and an Integer Linear Programming formulation of the mapping decision, along with iterative refinements of the solution for automated hardware/software co-design. Experimental results demonstrate the capability of our approach to consider complex designs and yet output near-optimal partitioning decisions.
All faculties and students are welcome to join.